Phase locked loops (PLLs) have been used for frequency synthesis in many conventional circuits, and these PLLs generally included internal and/or external dividers. These PLLs (and the corresponding dividers) have also been used to generate fractional frequencies, but, usually, at a price (namely, spurs and jitter). Therefore, there is a need for an improved fractional divider that can be used with or within a PLL or reference clock generator. There is also a need for an improved digital phase interpolator with improved linearity to be used in design of such fractional dividers and other circuits where intermediate finer phase steps need to be derived from the available clock phases.
Some examples of conventional circuits are: U.S. Pat. No. 6,617,909; U.S. Pub. No. 2005/0093594; U.S. Pat. Nos. 5,945,862; 6,114,914; 6,236,703; 7,295,077; 7,417,510; 7,596,670; and No. 7,764,134; Yang et al, “A High-Frequency Phase-Compensation Fractional N-Frequency Synthesizer.” IEEE International Symposium of Circuits and Systems”, 2005 ISCAS, May 23-26, 2005, pp. 5091-5094; Garlepp et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, May 1999, pp. 632-644; Garlepp et al., “A Portable Digital DLL Architecture for CMOS Interface Circuits”, IEEE 1998 Symposium on VLSI Circuits Digest of Technical papers, pages 214-215; Saeki, et al., “A 1.3-Cycle Lock Time, Non-PLL/DLL Clock Multiplier Based on Direct Clock Cycle Interpolation for ‘Clock on Demand’”; IEEE Journal of Solid-State Circuits, Vol. 35, November 200, pp. 1581-1590; and Chang et al., “A 0.7-2-GHz Self-Calibrated Multiphase Delay-Locked Loop”, IEEE Journal of Solid State Circuits, Vol. 41, No. 5, May 2006, pp. 1051-1061.